Parallel merging on the instruction systolic array

Abstract

In this paper the Instruction Systolic Array (ISA) is implemented using a soft systolic simulation system and a comparison given for the programming and simulation of a parallel merging program with the Processor Array (PA) and Instruction Broadcast Array (IBA). Finally the relationships between the ISA, IBA and PA VLSI computing structures are given.

Keywords:

• Instruction Systolic Array
• Parallel merging

C.R. Categories::

• C1.2
• F2.2