Integrated classifier simulator and neurochip VHDL implementation

O. B. Efremides Laboratory of Digital Systems, Section of Electronics and Information Systems Technology, Department of Electrical & Computer Engineering, School of Engineering Democritus University of Thrace, Thrace, Greece

M. P. Bekakos Laboratory of Digital Systems, Section of Electronics and Information Systems Technology, Department of Electrical & Computer Engineering, School of Engineering Democritus University of Thrace, Thrace, GreeceCorrespondence[email protected]

D. J. Evans Department of Computing, Faculty of Engineering & Computing, The Nottingham Trent University, Nottingham, UK

Abstract

In this work, the development of a simulator for a system capable of recognizing and classifying patterns into certain classes (families) is investigated. The classification system integrating hardware and software components is presented. The entire system simulator is developed using Java programming language, while its hardware parts are implemented and simulated using VHDL.

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Integrated classifier simulator and neurochip VHDL implementation

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Integrated classifier simulator and neurochip VHDL implementation

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