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Abstract
Folding transformations on processor arrays result in smaller processor arrays, more efficient work for the processing elements, a decrease in I/O time and pipelineable implementations. The regular folding procedure is realized to improve the efficiency of processor arrays whilst retaining the complexity of the data communications, the processor operations and the regular data flow. The efficiency analysis shows that the implementation obtained utilizes the processor array with double efficiency. Moreover by using the same processor array problems with double dimension can be solved. Also the circular data flow can be used for cascaded algorithms.