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Abstract
This paper presents two systolic algorithms for modular exponentiations based on a k-SR representation. In a systolic k-SR scheme, throughput is one modular exponentiation of a message block having n digits in every clock cycle, with a latency of nearly 5n/4 cycles to output the final result. The speedup for a group of messages having /message blocks is around (5\6l +2/3n), compared to a single processor or processing element for modular multiplications. The scheme saves nearly n/4 processing elements and around n/4 modular multiplications, compared with the scheme in [23]
The first author is supported by the ORS Award and the DTIIEPSRC LINK Personal Communications Programme project under UK EPSRC research grant GR/J17173
The first author is supported by the ORS Award and the DTIIEPSRC LINK Personal Communications Programme project under UK EPSRC research grant GR/J17173
Notes
The first author is supported by the ORS Award and the DTIIEPSRC LINK Personal Communications Programme project under UK EPSRC research grant GR/J17173