An efficient approach to mapping large anns onto fixed systolic architectures

Abstract

One of the best solutions to the communication problems arising in artificial neural networks (ANNs), due to the high interconnectivity of neurons, is achieved through their implementation on systolic array architectures (SAAs). The case of systematical mapping policies from ANNs to SAAs, however, is little explored. In this work, an efficient mapping policy is explored, capable of implementing an ANN on the available fixed systolic array, while it still allows the exploitation of the training pattern pipelined parallelism and remains feasible from the aspect of the hardware implementation cost.

Keywords:

• Artificial neural networks
• systolic arrays
• parallel processing
• pipelining
• VLSI architecture

C. R. Categories:

• B.7.1
• C.1.2
• C.1.3
• C.2.1
• F.1.1
• F.1.2
• F.2.1