General parallel structure digital repetitive control

Abstract

This article presents a parallel structure digital repetitive control (PSDRC) scheme, where the internal models of all harmonics are decomposed into multiple parallel connected groups. Compared with conventional repetitive controller, the proposed parallel structure enables repetitive controller to regulate the error convergence rate at each group of harmonic frequencies independently and offers faster total error convergence rate. Moreover, PSDRC can achieve zero-error tracking or perfect disturbance rejection for all harmonics without occupying more data memory. A stability criterion with rigorous proof for PSDRC system is addressed, which is compatible with those existing stability criteria for existing RC schemes. An application example of three-phase pulse-width modulation inverter is provided to demonstrate the effectiveness of the proposed PSDRC scheme.

Keywords:

• internal model principle
• repetitive control
• parallel structure
• stability criterion

Acknowledgements

We gratefully acknowledge the financial support provided by the National Natural Science Foundation of China (Grant No. 50977013). The comments provided by the reviewers are also gratefully acknowledged.