Small-scale reconfigurability for improved performance and double-precision in graphics hardware

Abstract

We explore the application of small-scale reconfigurability (SSR) to graphics hardware. SSR is an architectural technique wherein functionality common to multiple subunits is reused rather than replicated, yielding high-performance reconfigurable hardware with reduced area requirements (Vijay Kumar and Lach “Designing, scheduling, and allocating flexible arithmetic components”, in Proceedings of the International Conference on Field Programmable Logic and Applications, 2003). We show that SSR can be used effectively in programmable graphics architectures to allow double-precision computation without affecting the performance of single-precision calculations and to increase fragment shader performance with a minimal impact on chip area.

Keywords:

• Graphics hardware
• Computer architecture
• Reconfigurability

Acknowledgements

We would like to thank John Lach for his input on SSR and Peter Djeu for his collaboration on Chromium extensions. This work was funded by NSF grants CCF-0429765, CCR-0306404, and CCF-0205324.