Configurable and reconfigurable architectures offer the promise of substantial performance gains over more traditional computing architectures. These gains have been recognised by the ability of these architectures to implement directly in hardware specialised or customised operations or functions, and to tailor their internal architecture to meet applications’ specific computational and storage needs.
The extreme flexibility of configurable and reconfigurable architectures, either implemented by fine-grain reconfigurable devices such as Field-Programmable Gate-Arrays (FPGAs) or coarse-grain reconfigurable devices such as the commercially available PACT XPP processors, creates a set of very significant programming challenges. In order to effectively exploit the true potential of these devices, engineers must assume the dual role of software programmers and hardware designers. This continues to be the only way to bridge the semantic gap between the current set of compilers and hardware-oriented synthesis tools. It is in fact widely believed that the lack of a unified and effective programming model and development tools have hampered the widespread adoption of this technology in mainstream computing.
The Applied Reconfigurable Computing (ARC) workshop series has been devoted to addressing these challenges while still recognising the value of configurable computing basic techniques and application areas. We have thus recognised three major tracks at this workshop, respectively: architectures; applications; and tools. It has also been the aim of the workshop to bring together researchers in these three, often dissimilar, perspectives. This approach, we hope, will promote the synergy between them leading to better programming and application methodologies, or facilitating architecture discovery and early development of design and architecture evaluation methods.
In this special issue we have included three articles focusing on interesting architectural features and/or execution techniques which configurable architectures make more accessible. The first article, by Wu, Kanstein, Madsen and Berekovic, describes the application of multithreading to a coarse-grain reconfigurable architecture. The second article by Chikhi, Derrien, Noumsi and Quinton, is devoted to a specific architectural feature, the inclusion of FLASH memory to facilitate the implementation of image-based algorithms, an application that matches very well with FPGA configurable technology. Finally, a third article in this track by Hur, Wong and Vassiliadis, explores the use of point-to-point interconnects in a contemporary FPGA.
In the applications track we have included three articles. The first article by Beuchat, Miyoshi, Muller and Okamoto presents a survey of the implementation on FPGAs of multipliers based on Horner's rule for finite field arithmetic. Custom arithmetic has long been recognised a good target for the fine-grained FPGA devices and this survey article focuses on a specific domain, the Fpm. The second article, by Kim et al., describes the application of configurable computing to a very promising application area–health monitoring–where real-time response is critical. Lastly, the article by Diaz, Ros, Mota and Carrillo presents a crossover between architecture exploration and an image processing application, where the authors explore novel architectural features for local image feature processing, an important computation domain for configurable architectures.
The last four articles of this issue are devoted to tools whose goal is to make this promising technology more accessible to the average programmer, or simply to enable the expert programmer to reach a better architectural design quickly, by more easily navigating the inherent complexity of design space exploration exacerbated by the flexibility of configurable devices. The first article, by Jevtic, Carreras and Caffarena, focuses on modelling of switching activities for power estimation in FPGA multipliers. The second article, by Galuzzi, Bertels and Vassiliadis, explores the issue of instruction set selection by developing a linear complexity algorithm for finding multiple-input, multiple-output instruction templates. The article by Bispo and Cardoso addresses the issue of hardware synthesis of regular expressions with application to intrusion detection systems. Finally, the article by Park and Diniz presents performance modelling for FPGA implementation of windowing computation and its application in compiler mapping algorithms.
These articles are a sample of the many interesting papers presented at the ARC 2007 workshop, held in Mangaratiba, Rio de Janeiro, Brazil in March of 2007. We hope you find them interesting. We would like to take this opportunity to thank all the reviewers and the IJE staff for their help with this special edition volume.