A high-performance, low-area reconfiguration controller for network-on-chip-based partial dynamically reconfigurable system-on-chip designs

Abstract

Network-on-chip (NoC) has been identified as an attractive solution to the ever increasing interconnect problem in complex system-on-chip designs, particularly in those that include partial dynamically reconfigurable logic. To be integrated in NoC architecture, three issues for the design of a NoC-based reconfiguration system have to be considered at the same time. First, the processor cannot involve the entire reconfiguration process for the sake of NoC scalability. Second, NoC architecture as communication between IP cores is implemented by network protocols in NoC. Third, inclusion of reconfigurability into the chip demands additional chip area, besides the area penalty caused by the NoC itself. Tradeoffs between area and chip flexibility thus have to be carefully evaluated. In this article we describe a high-performance, low-area reconfiguration controller design that satisfies stringent performance and latency requirements. This proposed controller architecture is implemented at the transport layer, and all the operations related to reconfiguration are performed only on the network interface (NI) side to minimise the disturbance to the network performance. In addition, this NI also performs protocol conversions that are vital to ease the integration of IP cores obtained from various vendors using standard and/or propriety communication protocols. Experimental results with a Xilinx FPGA have confirmed the robustness and superiority of the proposed controller and the NI designs for NoC-based systems.

Keywords:

• network-on-chip
• reconfiguration controller
• network interface

Acknowledgement

This work is supported by NSF of China through grants (60706004) and (60876018).