Network-on-chip (NoC) is an emerging paradigm for communications within large very-large-scale integrated (VLSI) systems implemented on a single silicon chip. It is used as a new approach to design complex systems-on-a-chip (SoCs). NoC-based systems can accommodate multiple complex SoC designs. In a NoC-based system, modules such as processor cores, memories and specialised intellectual property (IP) blocks exchange data using an on-chip network.
A NoC is constructed from multiple point-to-point data links interconnected by switches also called routers, such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. VLSI designers of NoC-based systems face several problems, among which we can cite, for instance, planning the architecture that is most suitable to a given application in order to improve performance and mapping the sub-systems that form the application into the multiple tiles of the NoC infra-structure. Evolutionary computation as well as other computational techniques, can be used as a very robust tool to bring some answers to this kind of design problems.
This present special issue of International Journal of Electronics aims at presenting the latest advances that cover hardware, middleware and application designs and synthesis tools that exploit the evolutionary computation principles and other computational techniques to provide CAD tools and innovative designs for NoC-based systems. The main contribution of each of the included five papers is briefly introduced in the following.
In the first paper of the issue, entitled ‘Heterogeneous NoC design through evolutionary computing’, the authors explore the use of biologically inspired evolutionary computational techniques to design and optimise heterogeneous NoC architectures, where nodes of NoC-based chip multiprocessor (CMP) exhibit different properties such as performance, energy, temperature, area and communication bandwidth.
In the second paper, entitled ‘Power-aware multi-objective evolutionary optimisation for application mapping on NoC platforms’, the authors propose an innovative power-aware multi-objective evolutionary algorithm to perform the assignment and mapping stages of a platform-based NoC design synthesis tool. The optimisation is driven by the required area and the imposed execution time considering that the decision maker's is the power consumption of the implementation.
In the third paper, entitled ‘Designing fault-tolerant NoC router architecture’, the authors design a fault-tolerant NoC router architecture. The router is capable of receiving and transmitting a flit in four clock cycles. The design has scaled down the total failure rate. The synthesis of fault-tolerant architecture does not increase much the required hardware area with respect to the non-tolerant architecture. It also consumes less dynamic power than a Hamming-TMR based method.
In the fourth paper, entitled ‘Ray tracing on a networked processor array’, the authors engineer a parallel ray tracing application mapping on a mesh-based multicore NoC architecture. They also investigate the impact of an optimised ray tracing kernel and parallelisation strategies, varying the workload distribution statically and dynamically.
In the fifth paper, entitled ‘A high performance, low area reconfiguration controller for network-on-chip-based partial dynamically reconfigurable SoC designs’, the authors propose a high-performance yet low-area reconfiguration controller design that satisfies stringent performance and latency requirements. The proposed controller architecture is implemented at the transport layer, wherein all the operations related to reconfiguration are performed only on the network interface in order to minimise the disturbance to the network performance.
In the sixth paper, entitled ‘Migration selection of strategies for parallel genetic algorithms implementation on NoCs’, the authors investigate the impact of the migration strategies on the performance of a NoC-based implementation of parallel genetic algorithms. Two main strategies are considered: neighbourhood and ring.
Last but not the least, in the seventh paper, entitled ‘Building a multi-FPGA-based emulation framework to support NoC design and verification’, the authors present a highly scalable yet flexible hardware-based NoC emulation framework. In this framework, the NoCs infrastructure is built upon various types of network topologies, routing algorithms, switching protocols. Also, the tool allows for the exploration and comparison of several flow control schemes.
The guest editors are very much grateful to the authors of this special section and to the reviewers for their tremendous service by critically reviewing the submitted papers. The editors would also like to thank Prof. Ian Hunter, the Editor-in-Chief of the International Journal of Electronics; Taylor & Francis; and especially Dr. Alaa Abunjaileh for the editorial assistance and excellent cooperative collaboration to produce this scientific work. We hope that the readers will share our excitement with the papers included in this special issue on adaptive evolutionary computation and will find it useful.
N. Nedjah
Department of Electronics Engineering and Telecommunications,State University of Rio de Janeiro, Rio de Janeiro, Brazil
Email: [email protected]
A.H. Bouchachia
Department of Informatics-systems,University of Klagenfurt, Klagenfurt, Austria
L.M. Mourelle
Department of Systems Engineering and Computation,State University of Rio de Janeiro, Rio de Janeiro, Brazil