A power reduction technique for multi-modulus divider

Abstract

A new power reduction technique is presented for multi-modulus divider based on 2/3 divider cells. The ‘mod’ signals are employed to turn off the current of end-of-cycle logic blocks in 2/3 divider cells, when they have no contribution to the divider operation. An ideal multi-modulus divider adopting the power reduction technique is presented. Theory analyses show that the saved power percentage varies from 42.5% to 49% with division ratios changing from 256 to 8191 and the average saved power percentage is about 48.8%. As the division ratio becomes larger, the saved power percentage will be closer to 50%. An 11-bit multi-modulus divider based on this power reduction technique has been implemented in SMIC 0.18 um CMOS process. Theory analysis, simulation and test results show that the power reduction technique can save more than 39% power.

Keywords:

• multi-modulus divider
• power reduction technique
• 2/3 divider cell

Acknowledgement

This study is supported by the National Natural Science Foundation of China under no. 60676011.