Enhanced I_ON/I_OFF in ultra deep submicron CMOS devices using grooved nMOSFETs in comparison to planar nMOSFET

Abstract

To manage the increasing static leakage in low power applications and reducing ON‐OFF current ratio due to scaling limitations, solutions for leakage reduction as well as improving the current drive of the device are sought at the device design and process technology levels. At the device design level, the important low power variables are the threshold voltage, the gate leakage current, the subthreshold leakage current and the device size. Grooved‐gate MOS devices are considered as the most promising candidates for use in submicron and deep submicron regions as they can overcome the short‐channel effects effectively. By varying the corner angle and adjusting other structural parameters such as junction depth, channel doping concentration, negative junction depth and oxide thickness, leakage current in nMOS devices can be minimised. In this article, 90, 80, 70, 60 and 50 nm devices are simulated using Devedit and Deckbuild module of Silvaco device simulator. The simulated results show that by changing the structural parameters, ON‐OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is drastically reduced, as well as applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this study.

Keywords:

• planar MOSFET
• grooved MOSFET
• concave corner
• corner angle
• short‐channel effects
• deep submicron regime

Acknowledgement

The authors thank the VLSI Design Lab, ABV‐IIITM Gwalior for the help and support extended to them.