Interface circuit synthesis of system-on-chip

Abstract

Most of the intellectual properties (IPs) of system-on-chip (SoC) are provided by different vendors, and thus they may have various characteristics, making the interface circuit synthesis of SoC a time-consuming and error-prone process. The main contribution of this article is to present an interface synthesis algorithm for power minimisation in interface circuit design of SoC. Moreover, we also study the power and area trade-off in interface circuit synthesis of such systems. By starting from the power-minimal solution, we perform a sequence of power relaxation operations and area-minimising procedures to produce a set of solutions for a given SoC interface circuit design with power and area trade-off considerations. The experimental results demonstrate the effectiveness of our algorithms.

Keywords:

• system-on-chip
• interface synthesis
• power
• area
• optimization

Acknowledgements

The author thanks the anonymous reviewers for their helpful comments, which improved the quality of this article, and is also grateful for the support of Prof Yen-Tai Lai at the Casdc Laboratory of National Cheng Kung University, Tainan, Taiwan, ROC. This work was supported by National Science Council, Taiwan 97-2221-E-024-016.