A 200 MHz-to-1.4 GHz fast-locking pulse width control loop

Abstract

In this article, we propose a wide frequency range low lock time pulse width control loop (PWCL) circuit. The control stage of the PWCL with proposed frequency selection block can increase its output charge/discharge current at high frequency clocks. Therefore, narrow pulses can be generated at the output of this stage, which leads to the enhancement of the frequency range. Lock time of the circuit is also reduced, owing to the use of optimised second-order passive lead–lag loop filters instead of conventional loop filters. A 0.18-µm CMOS technology and 1.8-V supply voltage are used to verify the operation of the circuit. The simulation results show that the acceptable frequency range is from 200 MHz to 1.4 GHz, while maximum lock time of the circuit at this frequency range is about 580 ns. The proposed PWCL consumes 1 mW of power at 1.4 GHz.

Keywords:

• pulse width control loop (PWCL)
• second-order loop filters
• frequency to voltage conversion
• fast locking
• duty cycle correction