Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Abstract

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length L_g = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

Keywords:

• epitaxial delta-doped channel
• high-κ metal gate
• DIBL
• analogue and digital performances
• system-on-chip

Acknowledgement

The second author thanks the Department of Science and Technology, Govt. of India, for providing the infrastructural support through Fast Track Young Scientist Scheme (vide SR/FTP/ETA-0063/2009).

Additional information

Funding

Both the authors thank TEQIP Phase-II, University of Calcutta, for partial financial support of the research work (vide TEQIP-II/R&D/13/111(5)).