A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

ABSTRACT

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.

KEYWORDS:

• Analog-to-digital converter (ADC)
• time-interleaved
• successive approximation register (SAR)
• design-for-test
• foreground calibration

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

This research was supported by the 863 National High Technology Research and Development Program of China [2013AA011202] and National 02 Key Special Program [2009ZX02305-005], 863 National High Technology Research and Development Program of China [2013AA014102] and National No.2 Special Key Project Program [No.2012ZX02503005].