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Research Article

600-V shielded trench split-gate VDMOS improving the figure of merit

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Pages 1083-1097 | Received 18 May 2019, Accepted 28 Oct 2019, Published online: 20 Nov 2019
 

ABSTRACT

A shielded trench split-gate vertical double-diffused metal-oxide-semiconductor field-effect transistor (ST-SG-VDMOS) is proposed, and the analytical model for the main components of specific on-resistance (Ron,sp) is derived. The polysilicon vertical field plate (VFP) with the thick oxide layer in every trench modulates the electric field distribution to ensure no degradation of breakdown voltage (BV). Moreover, due to the strong assistant depletion effect caused by VFPs, Ron,sp is effectively reduced by increasing the doping concentration among trenches. Not only the gate is shielded from the drain bias by VFPs, but also the split-gate structure is adopted to reduce the specific gate-drain charge (Qgd,sp). When compared to the conventional VDMOS (C-VDMOS) in 600 V class, the simulation results by the technology computer aided design (TCAD) show that the Ron,sp and Qgd,sp in ST-SG-VDMOS decrease from 128.8 to 85.77 mΩ·cm2 and from 88.3 to 14.1 nC/cm2, respectively. Finally, the product of Ron,sp and Qgd,sp called as figure of merit is reduced by 89.4% in the ST-SG-VDMOS. The performance of ST-SG-VDMOS has been significantly improved when compared with C-VDMOS.

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

This work was supported by the Key Project of the National Natural Science Foundation of China [61531016 and 61831017] and Sichuan Provincial Science and Technology Important Projects under Grant: [2018GZ0139,2018GZDZX0001].

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