An improved PWM with simplified unified switched logic (USL) for RSC MLIs

ABSTRACT

Inevitability to reduce the size, cost and complexity of multilevel inverter (MLI) to evolve simplified RSC (Reduced switch count) MLIs has created diversified effects such as limited switching redundancies which further restricted modularity and flexibility of implementing PWM schemes. Among the PWM schemes of RSC-MLIs, modified reduced carrier (MRC) PWM with unified switching logic (USL) is the simplest and claims to be superior with the state of art in terms of implementation, line harmonic performance, imposing least controller computational burden (of 6.5 µS to realise a three-phase seven-level RSC-MLI) by adapting minimal carrier constraints. However, this is valid for sophisticated digital controllers such as dSPACE MicroLabBox, but not for low-end cost-effective controllers such as dSPACE1104 (imposing a computational burden of nearly 25 µS to control a single-phase RSC-MLI). Thus, this paper proposes an improved USL which adopts no carrier constraints and operates with less computational burden over the conventional USL. The proposed USL gives flexibility to the user to implement a part of the switching logic with analogue circuits and thereby avoid the requirement of high-end digital controller. The scalability and superiority of the proposed USL is demonstrated for symmetrical and asymmetrical configurations of popular cascaded T-type RSC-MLI. Efficacy of the proposed USL is demonstrated with dSPACE 1104 controller and dSPACE FPGA R&D Micro-lab Box.

KEYWORDS:

• Reduced Switching Count (RSC)
• Reduced carrier PWM
• Unified Switching Logic (USL)
• Multilevel Inverter (MLI)
• T–type topology

Disclosure statement

No potential conflict of interest was reported by the author(s).