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International Journal of Electronics Volume 38, 1975 - Issue 1
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Original Articles

A ternary flip-flop circuit

SHRI SUDARSAN RATH Department of Electrical Engineering Rourkela 8 R.E. College, Orissa
Pages 41-47 | Received 12 Nov 1973, Published online: 23 Feb 2007
 
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Abstract

The paper describes a Ternary flip-flop. The output is obtained in the form of three: levels of voltage corresponding to logic status 2, 1, 0, when triggered by 1 kHZ pulses.

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