A fully integrated all-enhancement PMOS four-quadrant analogue multiplier

K. K. CHI University of Cincinnati, Department of Electrical and Computer Engineering, Solid State Electronics Laboratory, Cincinnati, Ohio, 45221, U.S.A.View further author information

JOSEPH H. NEVIN University of Cincinnati, Department of Electrical and Computer Engineering, Solid State Electronics Laboratory, Cincinnati, Ohio, 45221, U.S.A.

Abstract

A PMOS four-quadrant analogue multiplier is described and performance is measured. The measured distortion is 0 · 9% at 50% of full-scale output and the dynamic range is 79 dB. The chip is compatible with standard IC processing and the circuit could be incorporated as a part of a more complex signal-processing die.

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K. K. CHI

Present address: Digital Equipment Corp., Hudson, Massachusetts 01749, U.S.A.

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A fully integrated all-enhancement PMOS four-quadrant analogue multiplier

Notes on contributors

K. K. CHI

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A fully integrated all-enhancement PMOS four-quadrant analogue multiplier

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Notes on contributors

K. K. CHI

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