Delay-Macromodelling Of Cmos Transmission-Gate-Based-Circuits

Abstract

Transmission gates are used extensively in CMOS VLSI circuits. However, very few delay models have been developed for transmission gates or transmission-gate-based circuits. Accurate delay models are presented in this paper and compared with delays obtained from SPICE simulations. These delay models are based on analytical expressions for the output voltage of the transmission-gate-based circuits in various regions of operation obtained from the mode of operation of MOS transistors that make up the circuit. The model-based output propagation delays and transition times are within 10% of SPICE-aimuIation-based delays for various capacitive loads and input transition times.

Keywords:

• VLSI
• Signal delay
• Modelling
• Macromodela
• Transmission gate
• Timing analysis