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Abstract
This paper describes a novel approach to the modelling of the multirate switched capacitance (SC) filters using the nonlinear programming with a series of equality constraints. The procedure optimally distributes a limited switched capacitance area in the input branches of individual SC filter, by minimizing the overall capacitor spread while simultaneously achieving a minimum total capacitor area. The optimization algorithm for dimensioning the constraints allows an iterative simulation to carry out the synthesis task, implemented in a sequence two-step design procedure. Compared to the previous design example of SC decimator, the redesign shows that at least 9.2% reduction of the total capacitance area, while maintaining the same frequency responses.
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Notes on contributors
P.N. Cheong
Phillip N. Cheong received his B.Sc. degree from the South University of Science and Technology, China, M.S. degree from the South China Normal University, China, and Ph.D. degree in electrical and electronics engineering from the University of Macau, Macau, China in 1986, 1989, and 2001, respectively. He is currently an associate professor of Computer Studies Program in Macau Polytechnic Institute, Macau, China. His research interests include computer-aided design of analogue-digital circuits and optimization algorithms.