VHDL Modeling and FPGA based Implementation of a Memory Efficient Huffman Decoder

Abstract

Very High Speed Hardware Description language (VHDL) based modeling of a memory efficient Huffman Decoder using two-bit clustering technique and Field Programmable Gate Array (FPGA) based implementation are presented here. The two-bit clustering technique not only improves memory efficiency but also helps in reducing symbol search time. For an experimental video data with Huffman codes for 32 symbols extended up to 13 bits, the entire memory space is shown to be reduced to a mere 52 words as compared to a normal 2¹³ = 8192 words i.e., an improvement in efficiency from 0.39% to 61.5%. The hardware design and rigorous logic and timing simulation have been carried out with the help of High level design and gate level tools. The technology independent nature of VHDL modeling helps in the realization of the design into any technology. The design and implementation has all the inherent advantages of FPGA and has applications in areas where data compression is desirable such as HDTV etc.

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Mohd Hasan

Mohd Hasan received BSc Engg degree in Electronics Engineering in 1990 from AMU Aligarh. Subsequently, he completed his MTech in Integrated Electronics and Circuits from the Indian Institute of Technology, Delhi in 1992. He joined Electronics Engg Dept, AMU, Aligarh as Lecturer in 1992. He became Reader in 1997. He then completed his PhD in low power architectures for signal processing and Telecommunications from the School of Engineering and Electronics, University of Edinburgh, UK in January, 2004, His research interests include Low power IC design for wireless communications, Reconfigurable systems etc.