Fault Tolerant Interconnection Network Design

ABSTRACT

Advances in parallel and distributed computing have made interconnection networks a potential networking alternative to meet the growing demands of high-performance computing. Multiple processors need to communicate with each other and with memory modules. Multi-stage interconnection networks (MINs) provide a communication medium in multi-processor system as they interconnect a number of processors and memory modules. Design of MIN has to meet ever better performance by providing more disjoint paths, low hardware cost, higher reliability, and rerouting capabilities tolerating any switch/link failures. New architecture of fault tolerant multistage interconnection network layout is proposed. Proposed layout is a multipath MIN providing four disjoint paths for all the source and destination pairs. It has full access and dynamic rerouting property under any switch/link failures. Collision problems are effectively handled by this dynamic rerouting capability by automatically changing their routing path during any switch/link faults. Proposed network design is highly reliable with higher fault-tolerant capability than other interconnection networks topologies. Evaluated terminal pair reliability for new layout is found to be higher than other MINs.

KEYWORDS:

• Disjoint paths
• Fault-tolerant networks
• Multistage interconnection network (MIN)
• Networks
• Terminal reliability

Acknowledgments

The authors gratefully acknowledge the facilities in the centre manifested by the Head of Reliability Engineering Centre, IIT Kharagpur, and expert professors for sharing their pearls of wisdom. The authors would like to thank the editor and anonymous reviewers whose helpful comments that significantly helped us in improving the presentation of the paper.

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

S. Rajkumar

S. Rajkumar received his BE degree (distinction) in ECE and ME degree in Industrial (distinction) from Anna University, India, in 2009 and 2011, respectively, and currently pursuing the PhD degree from the Indian Institute of Technology Kharagpur, India. His current research interests include reliability engineering, and computer networks.

E-mail: [email protected]

Neeraj Kumar Goyal

Neeraj Kumar Goyal is currently an associate professor in Reliability Engineering Centre, Indian Institute of Technology Kharagpur, India. He has received his PhD degree from IIT Kharagpur in Reliability Engineering in 2006. His areas of research and teaching are network reliability, software reliability, electronic system reliability, reliability testing, probabilistic risk/safety assessment, and reliability design. He has completed various research and consultancy projects for various organizations, e.g. DRDO, NPCIL, Vodafone, ECIL, etc. He has contributed several research papers to international journals and conference proceedings.

E-mail: [email protected]