Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology

ABSTRACT

A power and area efficient metal-oxide semiconductor field-effect transistor (MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is proposed and designed in TSMC 0.18 μm digital CMOS technology with supply voltage of 1.8 V. It is based on charge pump based technique to achieve the stage voltage gain of 2. Various capacitances are implemented by MOSCAPs (capacitance offered by the MOSFET), offering compatibility with cheaper digital complimentary metal-oxide semiconductor (CMOS) process in order to reduce the much required manufacturing cost. The proposed stage suffers from only linear gain error with full signal swing of 2 V peak-to-peak (p–p) differential. Using the proposed stage, un-calibrated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) for 10-bit, 100 MS/s pipelined ADC are 40.11 and 40.86 dB, respectively, which can be further increased by using a simple digital calibration technique. Comparison between the proposed stage and conventional operational amplifier based stage shows insensitivity towards capacitor mismatch along with power savings and design simplicity.

KEYWORDS:

• Charge pump
• Differential stage
• Digital CMOS technology
• Low area
• MOSCAP
• Opamp

ACKNOWLEDGMENTS

The financial support provided by Department of Information Technology, MoCIT (GOI) through SMDP-VLSI (Phase-II) project is gratefully acknowledged.

Additional information

Notes on contributors

Anil Singh

Anil Singh received the BTech degree in electronics and communication engineering from Kurukshetra University, Kurukshetra, India in 2000 and MTech degree from Thapar University, Patiala, Punjab, India in 2011 where he is currently pursuing towards his PhD degree. Prior to joining his master degree, he worked as a design engineer in VLSI industry from 2005 to 2009. His research interests include low power analogue-to-digital convertors and smart data convertors.

E-mail: [email protected]

Alpana Agarwal

Alpana Agarwal received the MSc and MTech degrees from IIT-Delhi, India in 1986 and 1988, respectively, and the PhD degree from Thapar University Patiala, India. She worked as a scientist at IC Design Group in CEERI-Pilani, Rajasthan, India from 1988 to 1996. In 1996, she joined Thapar University as a faculty in ECED where she is currently working as an associate professor. Her research interests include mixed signal designing, VLSI circuit and system design-synthesis and design automation.

E-mail: [email protected]