An FPGA-based design for power efficient low delay rate adaptive pacemaker using accelerometer and heart rate sensor

Abstract

This paper presents a power efficient, low delay and rate adaptive dual chamber pacemaker (PLRDPM) using heart rate and accelerometer sensor. In recent years, number of modifications have been done in the pacemaker design. However, design of an implantable device on an open source is still challenging. Through this paper, we are proposing a “proof of concept” for the design of PLRDPM on FPGA for improving the vital parameters: delay and power consumption. The proposed PLRDPM comprises of accelerometer and heart rate sensors to measure physical activity's effect on heart rate of the bradycardia patients. A rate adaptive pacing algorithm has been designed using two sensor’s data, to reduce the delay and power consumption. However, delay in the responses of various components in the circuitry produces an accumulative delay effect in any practical circuit. The delay and the power consumption for the proposed PLRDPM are found to be 2.82 ns and 9 mW, respectively.

Keywords:

• Rate adaptive pacemaker
• accelerometer
• pulse sensor
• Verilog

Disclosure statement

All of the authors have no conflict of interest to disclose.

Additional information

Funding

This research work is part of a DBT funded project named, “Neural Network based Pacemaker Design”.