Abstract
Satellite communication essentially needs ultrareliable, compact and fast electronic systems. For reliability digital communication is extensively used in space and satellite communications. In digital communication the analogue message, to be transmitted, is digitally encoded by an Analogue-to-Digital converter. The bits of digitally encoded message are known as information bits. Then before transmission, a number of ‘redundant’ bits is appended to the information bits for error detecting and correcting at the receiving end. The generation of these redundant bits is usually done sequentially by shift registers and logic gates. Such methods are time-consuming and hence uneconomic for space communication. Recently, methods have been developed whereby a large number of logic elements can be fabricated on a single chip of substrate. These ‘large scale integrated’ arrays are very fast, compact and cheap. Iterative and ‘cellular’ organization concept is particularly useful in such systems. In this paper the applicability of large scale integrated cellular arrays for generation of error correcting codes and for detecting errors in the received code-word has been discussed. It has been shown that a relatively simple array structure can be used for performing all GF(2n) operations and hence can be used for algebraic error detecting codes. Such arrays have the added facility that operations in GF(2m) (m⩾n)can also be carried out.