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Abstract
In this paper, we propose an Adaptive Deltamodulator (ADM) wherein the step size information is obtained by checking the output bit stream for a certain number of consecutive bits of the same polarity. The number of bits to be checked has been shown to be dependent upon the sampling rate and must be reduced as the sampling rate is reduced in order to obtain a good performance. An experimental coder is described which has an SNR greater than 26 dB over an input range of 33 dB at a clock rate of 32 kHz.
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Notes on contributors
C. V. Chakravarthy
CHAKRAVARTHY, C V(Dr): Born in September 1949, obtained BSc from Bangalore University in 1967, BE and ME from Indian Institute of Science, Bangalore in 1970 and 1972 respectively and PhD from IIT Kharagpur in 1977. He has been a lecturer in the Deptt. of E & ECE IIT, Kharagpur since 1975.
M. N. Faruqui
FARUQUI, M N (Dr): Born in 1934, obtained his BSc from University of Allahabad in 1952, BTech (Hons.), MTech and PhD degrees from IIT, Kharagpur in 1956, 1961 and 1965 respectively. He has been on the 'staff of the Dept. of E & ECE, IIT Kharagpur since 1958 where he is at present a Professor. He was at the Loughborough University, UK in 1976–77 where he was working on low-bit-rate speed coding. His areas of interest are digital communication and speech coding.