Performance Analysis of Pipeline Architecture

Abstract

Pipelining has emerged asa powerful technique for obtaining a high throughput rate. The paper analyses Pipeline Architecture reviewing many problems of Instruction Pipeline. The measure of effectiveness in executing a job on a pipelined processor is given by efficiency deduced from the space-time relationship. An expression for efficiency has been deduced when segment times are unequal.

Performance of Instruction Pipeline suffers when conditional branch instructions are present in a programme. An expression has been deduced relating efficiency with the number of procedural dependencies in a programme. The suitability of the programme for execution on a pipelined processor may be determined by dynamic measurement of instruction frequencies as suggested here.

Indexing Terms:

• Pipeline Architecture
• Computer Efficiency

Additional information

Notes on contributors

Anirban Basu

Basu, Anirban: Received BE from University of Calcutta in 1976 and MTech from University of Calcutta in 1979. Joined Computer Science Unit of the Indian Statistical Institute, Calcutta after passing MTech. Visited USSR in 1979–1980 for training on Computer Systems. His research interests are in Computer Architecture, Computer Performance Evaluation and Data Base Machines. He is a Member of the Institution of Engineers (India).