Interconnection Hardware for Distributed-Systems Communications Architecture

Abstract

Interconnection hardware strategies are overviewed in light of loosely-coupled computing systems. Bus issues, arbitration and communication principles are outlined with a direction towards future bus definition and standards. High bandwidth interconnection schemes using multi-port memory controllers and cross-point switches are presented followed by a specific design of a cross-point inter-connection switch. Future research in distributed computing is discussed, providing a comprehensive set of architectural and software issues.

Indexing Terms:

• Bus Architecture
• Communications Architecture
• Distributed Systems
• Distributed Processing

Additional information

Notes on contributors

M. Ganapathi

Ganapathhi, Mahadevan (Dr): Received BTech in Electronics * Elect. Comm. Engg. from IIT, Kharagpur in 1976; M.S. (Computer Science) in 1978, M.S. (Elect. * Computer Engg.) in 1979 and PhD (Computer Science) in 1980 from the Univ. of Wisconsin, Madison. His doctoral dissertation was on Automatic Compiler Code Generation.

At present, he is with the Computer Systems Lab, Stanford Univ., Calif. His research interests are in compiler construction and computer architecture.