Abstract
A microprocessor-based sequential docoder employing Fano's algorithm for rate-half non-systematic convolutional code of constraint length three is discussed. The decoder is implemented on the VMC-85 microprocessor kit, which employs the Intel 8085A as its CPU. The encoder is realized through a hardware external to the microprocessor. Fixed and random errors are added to test the performance of the sequential decoder. Tests with fixed errors show that the decoder can correct any two errors in sixcode bits. Experimental performance of the decoder for data transmission in the presence of random errors has been evaluated and it is found that BER is improved from 10−3 at the input to better than 10−6 at the output. A coding gain of 0.8 dB at BER of 10−5 has been achieved.
With the limited speed and limited memory of the microprocessor kit, it has been possible to achieve a data throughput rate of 600 bps. The microprocessor-based decoder would be useful in robust real-time data communication links up to a speed of 600 bps.
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B.S. Katakol
B.S. KATAKOL He was born in the year 1942. He received the B.E. degree in Electrical Engineering and M. Tech. degree in Industrial Physics from Karnataka Regional Engineering College Surathkal affiliated then to Mysore University. He was an Asst. Lecturer at B.V.B. Engineering College Hubli, during the years 1967–68 and served as Lecturer at University Visveswaraya College of Engineering Bangalore University, Bangalore and at KREC, Surathkal, from 1970 to 1973 and from 1973 to 1979 respectively. He is presently working as a Reader in Electrical Engineering at UVCE, Bangalore University, Bangalore and is on deputation at IIT, Kharagpur under the Quality Improvement Programme of Govt of India. He was responsible for a prize winning project financed by Karanataka State Council for Science and Technology. His areas of interest are Communication systems, Microwave Solid state Devices, Error Correcting Codes and special Communication systems suitable for fading channels.