Analysis of DC Current Gains in Lateral Transistors

Abstract

The dependence of the dc current gains of lateral transistors on the buried layer doping level and on the effective nn⁺ recombination velocity S_nn⁺has been analysed using a quasi-one dimensional model. The model takes into account the electric field in the retarding and the accelerating portions of the n⁺ subdiffused layer. Besides, it utilises the concept of an effective interface recombination velocity or transport velocity in analysing the hole transport in the vertical parasitic p-n-n+-p section. This adds to the simplicity of the present model.

The common emitter and common base dc current gains have been estimated for typical lateral transistor structures. The extension of the use of ‘effective’ lateral emitter and collector areas, previously defined for a device with an ideal nn⁺ interface (i.e., S_nn + =0₁ to transistors having non-zero S_nn +has been demonstrated. Results from the present model have been compared with those from previously published two dimensional analyses. The comparison shows that the present 'odel can give reasonable estimates of α and β for practical buried layer doping levels and for values of S_nn+as high as 10⁴ cm/sec. The latter result is of significance because of the wide range (10–10⁴ cm/sec) of S_nn⁺reported in literature.

Indexing terms:

• Lateral Transistor
• Doping Ratio
• Effective Recombination Velocity