Diagnostic Logic Graph for Testing MOS Circuits

Abstract

Conventional stuck fault model fails to detect every transistor stuck fault in a MOS circuit. This paper deals with the problem of generating test to detect such faults. The MOS circuit is represented by a graph termed as Diagnostic Logic Graph (DLG) which preserves the logic implemented by the circuit in addition to the relevant diagnostic information. An N or P-MOS transistor, bus line, pass transistor etc of a circuit are appropriately characterized by this graph model. Based on the analysis of DLG, an adaptive test generation procedure to cover all the faults in a circuit is proposed.

Indexing terms:

• Diagnostic logic graph
• Transistor faults
• MOS circuits