LPCVD Polysilicon SOI MOSFET Technology for 3-D Integration

Abstract

A review of the LPCVD polysilicon MOSFET Technology for 3-D integration is presented covering the influence of grain boundary and polysilicon thickness oil the MOSFET parameters, and the recent approaches to hydrogenation for passivating the grain boundaries. Both top gated and bottom gated SOI MOSFETs are discussed and the different modes of device operation suitable for 3-D integration are presented and compared.

Indexing terms:

• LPCVD Polysilicon MOSFET technology
• SOI MOSFETS
• MOS Integrated circuits