Latch-up Prevention in CMOS by Substrate Bias and Double Diffused Drain Technology

Abstract

The effect of substrate bias and double diffused drain (DDD) structure on latch-up, normally used as a preventive measure for latch-up suppression, have been modelled using a parasitic transistor base charge neutrality controlled graphical solution. The present technique seeks a model for the entire characteristics of the latch-up device rather than for a few sample points (eg trigger or hold point). SPICE simulator is used as an aid to obtain a graphical solution for the device characteristics. It is demonstrated that DDD structure is capable of providing some latch-up hardnesss while its implementation is fully compatible with the normal process flow. The model has been experimentally validated for the structures fabricated in 2 μm twin-tub CMOS technology.

Indexing terms:

• Double diffusion drain technology
• CMOS technology