On the Design of a Race Free CMOS Edge Triggered Flip Flop

Abstract

Edge triggered digital design, while simple at the conception stage compared to multiphase clocked design, is extremely complex from a timing design point of view. Clock skew insensitive design techniques suitable for VLSI are investigated and a race free CMOS edge triggered flip flop design is proposed. This flip flop finds application in clocking schemes that convert the two sided timing constraints of edge triggered design in synchronous systems into single sided timing constraints.

Indexing terms:

• Edge triggered Flip Flop
• VLSI systems