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Original Articles

GENESIS—A Standard Cell Based VLSI Design System

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Pages 259-264 | Published online: 02 Jun 2015
 

Abstract

This paper describes GENESIS, a Standard Cell based VLSI Design System. GENESIS was designed to be used on simple, slow machines such as IBM-PCs with little memory and low resolution graphics, though additional hardware can be used if available. Implementing a complete design system on these machines imposes servere constraints, particularly for interactive programs where response time is crucial. GENESIS consists of two sets of modules—one for designing a Cell Library, and another for designing chips (systems) using library cells. GENESIS has many original algorithms incorporated in it, including a new circuit extraction strategy, and original algorithms for placement, global routing and channel routing. It is being used as a teaching aid for graduate and undergraduate students in VLSI design courses at the Indian Institute of Technology, Delhi. The modular nature of GENESIS makes it useful as a vehicle for developing and testing new algorithms in a design environment. It also makes it facile to link new modules with it. A Systolic arrary compiler has been linked with GENESIS, enabling chips implementing a systolic algorithm specified by the user to be compiled.

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