An Ideal Simulator for Hardware

Abstract

The increase in the density of integrated circuits has raised the level of designs that can be implemented on a single chip. Consequently, CAD tools involved in these designs have to address issues ranging from system level to logic level design. This paper presents a new hardware description language, IDEAL, and the simulation strategy adopted for it. IDEAL, which forms the basis of the Integrated Design Automation System (IDEAS) project, supports hierarchical and modular descriptions of asynchronous and synchronous digital systems at various levels. The simulator for IDEAL is based on the coroutine model. A design is simulated by appropriately scheduling coroutines which model the design entities whose behaviours given in IDEAL. Translation of a behaviour into a coroutine involves the compilation of IDEAL's data transfer and data control constructs into ‘C’.

Indexing terms:

• Hardware description languages
• IDEAL
• simulation