On the Reconfigurability of Hardware Accelerators for VLSI CAD tools

Abstract

A hundred fold performance improvement of a CAD tool can bring about a similar increase in design size. Hardware accelerators for CAD tools offer such performance improvements, but are application specific. Though some accelerators can be programmed to adapt themselves to somewhat different applications, it takes as much time and money to reconfigure one as it does to purchase a new one. Hence the use and acceptance of hardware accelerators has been limited. To alleviate the above mentioned problem we demonstrate that a wide variety of problems in VLSI design, viz gate array placement, standard cell placement, PLA folding, channel routing can be mapped on to a single mother problem. From the solution to the mother problem, the solutions to the other problems can be deduced. Therefore, a single hardware accelerator to solve the afore mentioned mother problem along with a translator-deducer kernel to translate the various problems to the mother problem and again decipher the solution would be sufficient to solve a wide range of problems in VLSI CAD.

Indexing terms:

• VLSI CAD tools
• Hardware accelerators