A Simultaneously Testable PLA with High Fault Coverage and Reduced Test Set

Abstract

An improved design of easily testable programmable logic array, based on a set of product line grouping conditions, has been proposed. As a result of the grouping of the product lines the extra hardware due to shift register cells is reduced. Within each group the concept of simultaneous testing of a number of product lines has been applied that resulted in a substantial reduction of testing time. The product line partitioning conditions have been so designed that, in addition to detecting the faults that the existing techniques can detect, those faults that remained undetected in similar existing techniques are now ensured to be detected with the proposed technique. Therefore, the fault coverage has also been observed to increase. A new technique called “CP device counting” for sequencing the product lines within each product line group has also been introduced. This technique is simpler and requires less computational time than similar existing sequencing techniques. This technique when used in conjunction with the presented product line grouping and test vector generation techniques reduces the testing time even further.

Indexing terms:

• PLA
• Logic design
• Design for testability
• Fault detection