Novel Flexible Systolic Mesh Architecture for Parallel VLSI Implementation of Finite Digital Convolution

Abstract

The paper presents a fully systolic mesh architecture for high-speed implementation of finite digital convolution. The proposed structure is fully pipelined, and maintains regular, as well as local interconnections. It has achieved significant reduction in latency and increase in throughput rate over the existing structure with less than proportionate increase in the hardware. Apart from these, it requires a small cycle period and offers considerable saving of latches.

Indexing terms:

• Systolic architecture
• VLSI
• Digital convolution

Additional information

Notes on contributors

B K Mohanty

Basant Kumar Mohanty, born in Orissa on June 1, 1967. Received the BSc Degree in Physics from Sambalpur University, Orissa in 1987 & MSc Degree from Jyoti Vihar, Sambalpur University, in 1989. He Joined India Meterological Department (IMD) as a Scientific Assistance from 1st June 1992. Then joined Orissa Education Service (OES.) from 1st October, 1992 as a Lecturer in Physics at SKCG College, Parlakhemundi, Orissa. Started Research Work on Digital Signal Processing from 1993 and submitted the thesis at Berhampur University on September 1997. His research interest are Digital Signal Processing Efficient VLSI architecture for Digital Filters and adoptive filtering.

P K Meher

Pramod Kumar Meher, obtained his BSc, MSc and MPhil degrees from Sambalpur University in 1976, 1978 and 1981, respectively. He was awarded PhD degree by the same University in 1996 for his work in the field of Digital Signal Processing. He has worked as Lecturer in Physics during 1981 to 1993 in Gangadhar Meher College, Sambalpur and other government colleges in Orissa. He was Reader in Electronic Science in Berhampur University during 1993 to 1997. Presently, he is Professor and Head of the Department of Computer Science and Application, Utkal University. Dr Meher's name is included in the Marquis Who's Who in the World, 1998. He has several research papers in various national and international journals and conferences. His research interest includes soft computing for forecasting problems, mobile computing, adaptive signal processing and VLSI architecture for high performance computing.