Polysilicon Piezoresistive Pressure Sensors based on MEMS Technology

Abstract

Polysilicon piezoresistors configured in a Wheatstone bridge, have been fabricated over a silicon diaphragm of 25 to 100 microns thickness for pressure sensing in a range of mbar to tens of bar. A suitable integration of the microelectronics steps with the MEMS technology, has been developed for the fabrication of chips in batches. The developed fabrication process is competent to provide nearly 80 chips of 4 × 4 mm² size on a two inch diameter silicon (100) wafer with polished surfaces.

Indexing terms:

• MEMS
• Polysilicon piezoresistors
• Bulk micromachining

Additional information

Notes on contributors

J Akhtar

J Akhtar was born in Ghaziabad in 1959. He received BSc (Hons) and MSc degrees in Physics with specialization in Electronics in 1977 and 1980 respectively. During the period he joined Bharat Electronics Ltd. (BEL) Ghaziabad, for a short period, at the post of Planner B.

From 1980 to 1983, he worked at CEERI, Pilani, first as Junior Research Fellow and then Senior Research Fellow of CSIR for his PhD thesis work on “Study of Two- Dimensional Breakdown Phenomena in semiconductor Devices”.

Since 1983, he has been associated with Semiconductor Devices Area of CEERI, Pilani, as Scientist. At present he holds the grade of Scientist-Ell. During the period he has been deputed at Technical University of Munich, Germany, for the year 1991–92, under DAAD fellowship programme. From 1998 to 2001, he also stayed at School of Physical Sciences at JNU New Delhi as research fellow. In 2002, he was awarded a project under New Idea Fund Scheme of CSIR on “MeV ion induced recording in single crystalline silicon; viability for device applications”.

His research interest includes; technology for silicon based IMPATTs and BARITTs for x-band and w-band applications, Numerical techniques for semiconductor device simulation, Design and fabrication of Microstrip detectors, Design and fabrication of piezoresistive pressure sensors based on MEMS technology and MeV ion assisted techniques for nanostructure formation in single crystalline silicon. He has also contributed to GaAs based technologies for high frequency devices at TU Munich and STM / AFM analysis of nanostructures at SPS / JNU.

He has strong collaboration with nanoparticle laboratory at SPS / JNU and Material Research Group at NSC, New Delhi.

He holds four patents to his credit and twenty papers in international journals. A number of papers have been presented in international / national conferences. He is a life member of Indian Physics Association and of IETE, India. He is a member of IEEE, USA.

B D Pant

B D Pant is MSc (Physics) from Kumoun University, Nanital and ME (Microelectronics) from BITS, Pilani. He started his career with-CEERI in 1980 by joining a project for the process development of high power Piezoelectric ceramic materials. Afer the successful process development, he switched over to silicon semiconductor fabrication technology in 1984. As a member of IC fabrication team he successfully fabricated a number of LSICs such as 8-bit binary counter chip. Later, in 1985, he was associated with the establishment of Dry Processing Facility. In early 90s he has established a dry etching facility for the reactive ion etching of metallic layers (AI AISi and AlSiCu) for the fabrication of VLSICs. He has developed a number of plasma etching processes for dielectric, semiconducting and metallic layers for IC fabrication. His current interests are in MEMS and Microsensors, where he is working on a number of projects related to technology and device development. He has approximately 31 conference / journal papers, 12 research reports, two patents and contribution of a chapter to a book titled “Patterning of Material Layers in Submicron Region” published by John Wiley, to his credit. He is a life member of Semiconductor Society of India, Indian Physics Association, Indian Vacuum Society, Indo-French Technical Association and fellow of IETE, India.

V P Deshwal

V P Deshwal received the BE (Hons) degree in Electrical Engineering from Birla Institute of Technology & Science, Pilani, India in 1970. He had been to General Electric Company, Schenectady, NY, Westing House, youngwood, Pittsburgh, USA, under UNDP project for an advanced study in Solid State Devices from May 1979 to January 1980. His research experience includes plasma enhanced and low pressure chemical vapour deposition of interlevel dielectrics and tungsten for multilevel interconnect technology for LSI/VLSI; packaging, encapsulation and metalisation for semiconductor devices. He has contributed substantially in the design and development of To-series semiconductor for packages for encapsulating transistors, IC chips which are being manufactured on the basis of their know-how.

He has also worked on the design and development of silicon transistors, darlington power transistors and test patterns for their evaluation. At present he is engaged in research and development of pressure sensors using silicon and micro-machining techniques and development of thin depositions using rapid thermal processing system at Central Electronics Engineering Research Institute, Pilani, India as Scientist-Ell. He is Fellow of IETE, Life Member of Semiconductor Society (India).