A Low Power Architecture for a MC-CDMA Receiver

Abstract

Multi-carrier code division multiple access (MC-CDMA) has a lot of potential in future generations of mobile communications and hence power consumption is important. This paper proposes a pipelined low power architecture for a 64 sub-carrier MC-CDMA receiver. The receiver comprises of two blocks namely the FFT for demodulation of the OFDM signals and a Combiner for de-spreading and equalization. The 64-point FFT block is based on a low power pipelined radix-4 architecture in which order based processing is applied to its second stage to further bring down Its power consumption. The power saving also occurs in the Combiner by disabling the unused blocks through clock gating and also by using a summer and a complementor rather than an adder/subtractor module.

Indexing terms:

• MC-CDMA
• FFT
• OFDM
• Low power

Additional information

Notes on contributors

M Hasan

Mohd Hasan received the BTech degree in Electronics Engineering in 1990 from AMU, Aligarh. Subsequently, he completed his MTech in Integrated Electronics and Circuits from the Indian Institute of Technology, Delhi. He joined Electronics Engineering Department, AMU, Aligarh as Lecturer in 1992. He became Reader in 1997. He then completed his PhD in “low power architectures for signal processing and Telecommunications” from the School of Engineering and Electronics, University of Edinburgh, UK. His research interests include low power IC design for wireless communications, reconfigurable systems on FPGA's etc.

T Arslan

Tughrul Arslan is a Professor in the School of Engineering and Electronics in the University of Edinburgh. He is a member of the Integrated Systems Group and leads the System Level Integration activity. His research interests include: Low Power Design, DSP Hardware Design, Systemon-Chip (SoC) Architectures, Evolvable Hardware, and the use of Genetic algorithms in Hardware design issues. He is the principal investigator in a number of projects funded by EPSRC, DTI, Scottish Enterprise together with a number of industrial partners. Prof Arslan serves on the technical committee of a number of international conferences including the International Symposium on Circuits and Systems (ISCAS), and the Annual ASIC/SoC, and NASA/DoD on Evolvable Hardware.

J S Thompson

John S Thompson received his BEng and PhD degrees from the University of Edinburgh in 1992 and 1996, respectively. Since September 1999, he has been working as a lecturer in what is now the School of Engineering and Electronics at the University of Edinburgh. His research interests include estimation theory, signal processing algorithms and antenna array techniques for wireless communications. He has 60 publications to date and is currently an honorary editor of IEE Proceedings on Vision, Image and Signal Processing.