Finite State Machine Decomposition for Low Power

Abstract

This paper presents a Genetic Algorithm based strategy to partition Finite State Machine (FSM) into two disjoint FSMs, such that the bigger partition can be kept deactivated most of the time. The resulting power saving is found to be much higher than the works reported in the literature.

Indexing terms:

• FSM
• Low power
• Decomposition

Additional information

Notes on contributors

Santanu Chattopadhyay

Santanu Chattopadhyay received his BE degree in Computer Science and Technology from Calcutta University (BE College) in 1990. He received MTech in Computer and Information Technology and PhD in Computer Science and Engineering from IIT Kharagpur in 1992 and 1996 respectively. He is currently an Associate Professor with the department of Electronics and Electrical Communication Engineering, IIT Kharagpur. His research interest include low power VLSI design, Electronic CAD, testing, system-on-chip design and testing.

P Nagamaheswara Reddy

Palem Nagamaheswara Reddy received his BTech degree Computer Science and Engineering from KSRM College of Engineering Cuddapath, India. He received his MTech degree in Computer Science and Engineering from NT Guwahati, 2003. He is currently working as Assistant Systems Engineer in TA Consultancy Services. His research interests include Fini State Machines and Low Power Technologies.