Performance and Error Analysis of the Algorithms for Analog to Multi-Valued Digital Conversion

Abstract

Generalised successive approximation algorithms for analog to multi-valued digital conversion with uniform quantization were published in an earlier paper by the same authors.

In this paper, the information content in the output of the algorithms is determined. The results are used to derive an expression for a figure of merit of the algorithms. The figure-of- merit is the basis of generalised implementation architectures.

Also, the analysis of the behaviour of the generalised algorithms in the presence of comparison error is presented. General strategies for A/D conversion error correction are developed based on the analysis results.

Indexing terms:

• Multi-valued logic
• Analog-to-digital conversion
• Successive approximation

Additional information

Notes on contributors

A S Gandhi

Abhay S Gandhi was born in 1967 and did BE (Electronics Engineering) in 1989 from Visvesvaraya Regional College of Engineering (VRCE), Nagpur (Nagpur University). He did ME (Electrical Commn Engg) from the Indian Institute of Science, Bangalore in 1991. After working for three years in industry and teaching, he joined VRCE Nagpur as lecturer in July 1994. He has completed PhD in August 2002. He has published papers in IEEE sponsored international conferences and IETE journal. The areas of his teaching and research are circuits and system, digital communication and computer networks, wireless communication. He has also conducted seminars and published articles on PC hardware and related topics. He was executive committee member of IETE sub-center at Nagpur.

A M Dighe

Ashok S Dighe was born in 1942, did BSc (Engg) (Electrical) in 1965 from SGSIT, Indore. Later he completed ME in 1970 from the same institute. He joined Visvesvaraya Regional College of Engineering, Nagpur in 1970 as lecturer and retired from the same college as professor in December 2001. He completed PhD in 1994. Currently, he is professor-in-charge of research and consultancy at Yashwantrao Chavan College of Engineering, Nagpur.

He has a very vast teaching, research and consultancy experience. He has published several papers in IEEE sponsored conferences and journals. He has successfully developed several instrumentation solutions for the industry. He has worked as Dean (Academic Affairs) for VRCE, Nagpur (1995–1998) and head of the Department of Electronics and Computer Science at VRCE (1998–2001).

He is a recipient of research grants of AICTE on patentable technologies based on a System-on-chip project submitted to AICTE. The department of electronics and communication at YCCE has been sanctioned DST grants for a project based on SoC for VLSI facility development. He is associated with this project also.