A Subthreshold Surface Potential and Drain Current Model for Lateral Asymmetric Channel (LAC) MOSFETs

Abstract

A drift-diffusion theory based subthreshold drain current model for lateral asymmetric channel (LAC) MOSFET is presented. In this, an accurate analytical subthreshold surface potential model, in which the contribution of the varying depth of the channel depletion layer due to source and drain junctions have been accounted for is used. A physically-based empirical modification of the channel conduction layer thickness, originally proposed for relatively long-channel conventional devices, is also made for such short-channel asymmetrically doped devices. Very good agreement of both surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical simulation using Dessis of ISE-TCAD. The performance prediction of the subthreshold analog circuits based on this model is also found to agree well with that by the numerical simulator.

Indexing terms:

• Conduction layer thickness
• Depletion layer depth
• Lateral asymmetric-channel MOSFETs
• Subthreshold surface potential
• Subthreshold drain current

Additional information

Notes on contributors

S Baishya

Srimanta Baishya received the BE degree in Electrical Engineering from the Assam Engineering College, Guwahati, India and MTech degree in Electrical Engineering from the Indian Institute of Technology (IIT), Kanpur, India, in 1989 and 1994 respectively. He is currently pursuing PhD degree at Jadavpur University, Kolkata, India.

He is currently an Assistant Professor in the Department of Electronics & Telecommunication Engineering, National Institute of Technology (NIT), Silchar, India. His research interests include the MOS physics and modeling, technology and characterizations.

He is a member of IEEE.

S Chakraborty

Saurav Chakraborty received the BTech degree in Electronics & Communication Engineering from Kalyani Government Engineering College, Kalyani University, Kalyani, India in 2002. He is currently pursuing PhD degree at Jadavpur University, Kolkata, India.

He is presently a Research and Development Engineer of Embedded System in Simplex Infrastructures Limited, Kolkata, India. His research interest includes MOS physics, technology, characterization and circuit design.

A Mallik

Abhijit Mallik received the MSc degree in Electronics Science from the Calcutta University, Calcutta, India and PhD degree in Electrical Engineering from the Indian Institute of Technology Bombay, India in 1989 and 1994, respectively. His doctoral thesis was on the study of reoxidised nitrided oxide MOS devices for radiation-hard applications.

He played a key role in developing a radiation hard chip going up to 1 Mrad(Si) at the IIT Bombay. He was a Postdoctoral Fellow with the Department of Electrical Engineering, Yale University, New Haven, USA from 1994 to 1995, where he worked on the process development and interface characterization of jet vapor deposited (JVD) silicon nitride as an alternative gate insulator for ULSI applications.

He is currently an Assistant Professor in the Department of Electronics & Communication Engineering, Kalyani Government Engineering College, Kalyani, India. His research interests are in the area of physics, technology, characterization and modeling of CMOS devices.

Dr Mallik is a senior member of IEEE and is currently the vice-chairperson of IEEE EDS Calcutta Chapter.

C K Sarkar

Chandan Kumar Sarkar received his MSc degree in physics from the Aligarh Muslim University, India, the PhD degree from Calcutta University, Kolkata, India, and the DPhil Degree from the Oxford University, UK, in 1975, 1979, and 1983 respectively.

He was a research fellow of the Royal exhibition of 1851 at the Clarendon Laboratory, Oxford University, from 1983 to 1985. He was also a visiting fellow at the Linköping University, Sweden. He joined Jadavpur University, Kolkata, India in 1987 as a Reader in Electronics & Telecommunication Engineering (ETCE) and became Professor and Head at the Physics Department of the Bengal Engineering College (deemed University), Howrah in 1996. Since 1999 he has been a Professor and now Head of the ETCE department, Jadavpur University. He served as Visiting Professor in many Universities and has published around 100 papers in referred journals. He is also a distinguished Lecturer of the IEEE EDS.

Dr sarkar is a senior member of IEEE, a fellow of IETE and is the Chair of the IEEE EDS Chapter, Calcutta Section, India.