Scaling of Strain-Engineered MOSFETs

Abstract

The aim of the present work is to study the evolution of Si based heterostructure MOSFETs via the incorporation of new materials, for example strained-Si, and to predict the resultant device performance and scaling trends of strained-Si/SiGe MOSFETs for RF applications. The article describes a comprehensive technology CAD (TCAD) based methodology to design and optimize strained-Si channel of CMOS technology using Sentaurus tools. Sentaurus-PROCESS is used to simulate and optimize a typical 90/45-nm process flow, including channel, halo, source/drain (S/D) profile engineering, oxidation, deposition, etching, and annealing for dopant activation. The structure generated by Sentaurus-PROCESS is then simulated using the device simulator Sentaurus-DEVICE. The simulation results have been benchmarked with reported experimental strained-Si channel MOSFET device results. The calibrated n- and p-type devices are scaled down to a 45 nm gate length to assess the device and circuit behavior.

Indexing terms:

• Strained-Si
• Substrate-induced strain
• Virtual wafer fabrication
• Self-heating

Additional information

Notes on contributors

T K Maiti

Tapas Kumar Maiti obtained MSc degree with gold medal in Physics from the Vidyasagar University in 2005. He is currently working in IIT Kharagpur. His current research interests include the TCAD modeling and characterization of nano MOSFETs.