Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack

Abstract

Stacking of MOS transistors is used for minimization of leakage current in nano-scale Complementary Metal Oxide Semiconductor (CMOS) circuits. Stack arrangement of P-Channel Metal Oxide Semiconductor (PMOS) is preferred over N-Channel Metal Oxide Semiconductor (NMOS) because value of leakage current in PMOS is lesser as compared to NMOS. It results as the mobility of holes in PMOS is lesser than mobility of electrons in NMOS. This paper leads us to an observation of leakage current consumption by series/parallel combination of PMOS/NMOS transistors. This observation results in the development of novel circuit technique for reduction of leakage current in series/parallel PMOS/NMOS assembly. The effect of V_GS, V_DS, V_SB and intermediates node voltages is also addressed. The proposed circuit is simulated for Model file BSIM 3 Ver.3.1, TSMC 0.18 μ technology using Spice© simulator.

Keywords:

• Active mode
• Leakage current
• Transistor stacking
• Standby mode

Additional information

Notes on contributors

Vaibhav Neema

Vaibhav Neema was born India on December 31, 1979. He completed Master degree of Technology (M.Tech.) in Microelectronics from Punjab University Chandigarh, India and has been further specializing by pursuing Ph.D. under supervision of Dr. Sanjiv Tokekar development of low power design techniques as broad area of research from Institute of Engineering & Technology, Devi Ahilya University, Indore, India. He is also Lecturer in Electronics & Telecommunication Engineering Department Institute of Engineering & Technology, Devi Ahilya University, Indore, India. He has having more than seven years of teaching experience with various prestigious University/Institutes of India. He has more than 12 research publication in various pre-reviewed journal and conferences. He also chaired a technical session in ICEDSA’2010 held in Malaysia. E-mail: [email protected]

Shailesh Singh Chouhan

Shailesh Singh Chouhan was born in Indore (MP), India in 1978. He received M.E. degree in Electronics Engineering, Spl.Digital Communication Institute of Engineering & Technology, Indore, India in 2006. Currently, he is an lecturer for Department of Electronics and Telecommunication Engineering, Institute of Engineering & Technology, Indore (MP),India and continuous working in VLSI field. His research interest is Design and Development of low power high speed configurations for portable devices E-mail: [email protected]

Sanjiv Tokekar

Sanjiv Tokekar received his Bachelor of Engineering, (Electronics) , Master of Engineering (Applied Electronics) and Ph.D, (Electronics Engineering) from Devi Ahilya University (formerly known as University of Indore), Indore, India in the years 1982, 85 and 96, respectively. He has more than 27 years of experience in teaching. Currently, he is working as a Professor and Head Department of Electronics and Telecommunication in Institute of Engineering and Technology, Devi Ahilya University Indore, MP, India. More than 60 research papers are there in his credit. He is a senior member of IEEE, member of Computer Society of India, Indian Society of Technical Education. He also chair of IEEE MP subsection under Bombay section. His teaching and research area are VLSI, Computer Networks, Telecommunication Networks, Computer Architecture, Digital Signal Processing, Performance Evaluation of Computer Systems. E-mail: [email protected]