A 3.0–10.0 GHz UWB Low-Noise Amplifier with Forward Body bias Technique

ABSTRACT

An ultra-wideband (UWB) low-noise amplifier (LNA) based on cascaded common source stage with shunt–shunt resistive feedback architecture is proposed. The wideband input impedance matching is accomplished by shunt–shunt resistive branch with inductor degeneration and parallel resistor-inductor-capacitor (RLC) load, forming two parallel RLC branches having inherently two wideband band-pass filter characteristics, resonating both at lower frequency and higher frequency. The output matching is achieved via a shunt inductor and a series resistor without the use of a buffer. Additionally, both series and shunt-inductive peaking techniques are employed in the proposed UWB LNA circuit design for bandwidth extension. To reduce the supply voltage headroom consumption, the forward body bias technique is also employed in the proposed topology. The resistor-capacitor (RC)-extracted results obtained in this paper are competitive in comparison with recent reported work in appreciating good noise figure (NF) performance as well as low-voltage headroom consumption. In the post-layout simulation results, the proposed complementary-metal-oxide-semiconductor (CMOS) UWB LNA dissipates only 13 mW while achieving the S11 below −11.4 dB, S22 below −11.7 dB, a flat S21 of 11.5 ± 0.6 dB, a maximum NF of 3.48 dB, within the range of 3.04 – 3.48 dB over the 3.0–10.0 GHz band of interest. Moreover, the IIP3 is within the range of −6.3 to −7.8 dBm, P1 dB of −14.7 to −16.8 as well as the K-factor of above 1 throughout the entire bandwidth operation, attesting the fact that the resistive feedback circuit is stable. The chip area consumption is approximated to 0.997 × 0.933 mm².

KEYWORDS:

• CMOS
• forward body bias
• low-noise amplifier (LNA)
• shunt-shunt resistive feedback
• ultra-wideband (UWB)

Acknowledgements

This research is sponsored by the Minister of Science, Technology and Innovation of Malaysia under E-science Project 03-01-03-SF0783.

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

K. L. Soon

K. L. Soon is currently pursuing his BSc (electrical engineering) degree from the University of Malaysia. His current research interest includes analogue integrated circuit design.

Email: [email protected]

H. Ramiah

H. Ramiah received his BE, MS and PhD degrees in electrical and electronics engineering, majoring in analog and digital IC design from the University of Science, Malaysia, Penang, Malaysia, in 2000, 2003 and 2009, respectively. In the year 2003, he was with SiresLabs Sdn. Bhd, Cyberjaya, Malaysia, working on audio pre-amplifier for MEMs ASIC application and the design of 10 Gbps optical transceiver solution. In year 2002, he was with Intel Technology Sdn. Bhd., Penang, Malaysia performing high-frequency signal integrity analysis for high-speed digital data transmission and developing Matlab spread sheet for Eye diagram generation, to evaluate signal response for FCBGA and FCMMAP packages. Currently, he is a senior lecturer in the Department of Electrical Engineering, University Malaya. He was the recipient of Intel Fellowship Grant Award, from 2000 to 2006. His research work has resulted in several technical publications. His main research interest includes analog integrated circuit design, RFIC design and VLSI system design.

E-mail: [email protected]

Y. Y. Tey

Y. Y. Tey received his BSc (electrical engineering) degree from the University of Malaya, Kuala Lumpur, Malaysia, in 2013. He is currently pursuing his Master's degree in the University of Malaya with the research interest of analogue IC design specialized in ultra-wideband low noise amplifier.

Email: [email protected]