A 2D Potential Based Threshold Voltage Model Analysis and Comparison of Junctionless Symmetric Double Gate Vertical Slit Field Effect Transistor

ABSTRACT

In the present paper, a two-dimensional (2D) potential-based analytical model of threshold voltage for junctionless symmetric double gate vertical slit field effect transistor (JL SDG VeSFET) is developed. The proposed model is based upon the solution of 2D Poisson's equation and is also extended to consider the effect of third dimension on threshold voltage of the device. The model includes the effect of various device parameters such as geometric gate length, dielectric thickness, substrate doping, and metal gate work function on threshold voltage, and is compared with conventional metal oxide semiconductor field effect transistor (MOSFET) device in order to show better performance of junctionless transistor and its application for future low power very large scale integration (VLSI) circuits. The analytical model is assessed with 2D TCAD Sentaurus simulation. The analytical model not only provides useful physical insight into the subthreshold behavior of the device, but also offers basic design guideline to better exploit its scaling potential for future nanoscale devices. It has been reported that the proposed model is in good agreement with simulative analysis with only a marginal deviation of about 3% for various device parameters.

KEYWORDS:

• 2D analytical model
• Central potential
• Dielectric thickness
• JL SDG VeSFET
• Scaling
• Surface potential
• Threshold voltage
• V_th roll-off
• Work function

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Tarun Chaudhary

Tarun Chaudhary received BE degree in Electronics and Communication engineering from UIET, Panjab University, Chandigarh, in 2010. She received MTech degree in VDAT from NIT Hamirpur, HP, India. She is currently pursuing her PhD degree at NIT Hamirpur, HP, India. Her research interests include modeling and simulation of nanoscale devices.

E-mail: [email protected]

Gargi Khanna

Gargi Khanna obtained her BTech degree in Electronics and Communication engineering from REC Hamirpur, HP, India in 1997. She did her ME degree from PEC Chandigarh, India in 2002. She was awarded PhD degree from NIT Hamirpur, HP, India in 2012. Presently, Dr. Khanna is working as associate professor in Electronics and Communication Engineering Department at NIT Hamirpur, HP, India. Her area of research is Low Power VLSI Design. Dr. Khanna is a member of ISTE and IEEE. She has 10 research papers in international journal of repute and over 55 papers in national and international conferences.

E-mail: [email protected]